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ht46r63/ht46c63 a/d with lcd type 8-bit mcu rev. 1.90 1 may 17, 2004 general description the ht46r63/ht46c63 are 8-bit, high performance, risc architecture microcontroller devices specifically designed for a/d product applications that interface di - rectly to analog signals and which require lcd inter - face. the mask version ht46c63 is fully pin and functionally compatible with the otp version ht46r63 device. the advantages of low power consumption, i/o flexibil - ity, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, halt and wake-up functions, in addition to a flexible and configurable lcd interface enhance the versatility of these devices to control a wide range of applications re- quiring analog signal processing and lcd interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc., for both industrial and home appliance application areas. features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v operating frequency: external rc or crystal 32.768khz crystal oscillator used for timing purposes watchdog enable or disable function 1x16 bits timer with an overflow interrupt (tmr) time base generator (clock source: 32.768khz) and rtc interrupts 4k 15 program memory 208 8 data memory ram maximum of 32 i/o lines (shared with int0 , int1 , tmr, an0~an7, pwm0~pwm3) 8-level stack up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 2 external interrupts (high/low going trigger) one comparator lcd: 20 3or19 4, 1/3 bias with 12 pins logical outputs options. (select by options in unit of 4 pins, 8 high sink) built-in r type bias generator 8 channels 8-bits resolution a/d converter 4 channels pwm outputs 56-pin ssop, 100-pin qfp package
block diagram ht46r63/ht46c63 rev. 1.90 2 may 17, 2004
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pin assignment ht46r63/ht46c63 rev. 1.90 3 may 17, 2004
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pad assignment ht46c63 * the ic substrate should be connected to vss in the pcb layout artwork. pin description pin name i/o option description pa0~pa7 i/o pull-high wake-up i/o lines with pull-high resistors (bit option). i/o modes of each line are con - trolled by related control register bit (pac). each line of pa can be optioned as a wake-up input (bit option). i/o configurations: schmitt trigger/cmos pb0/an0~ pb7/an7 i/o pull-high i/o lines with pull-high resistors (bit option). i/o modes of each line are con - trolled by related control register bit (pbc). i/o configurations: schmitt trig - ger/cmos. each pb line is pin shared with an a/d converter input. pc0~pc6, pc7 i/o pull-high i/o lines with pull-high resistors (bit option). i/o modes of each line are con - trolled by related control register bit (pcc). i/o configurations: schmitt trig - ger/cmos. pd0/pwm0~ pd3/pwm3, pd4/int0 , pd5/int1 , pd6/tmr, pd7 i/o pull-high pwm interrupt falling and/or rising i/o lines with pull-high resistors (bit option). i/o modes of each line are con - trolled by related control register bit (pdc). i/o configurations: schmitt trig - ger/cmos. the pd0~pd3 can be selected as pwm outputs. int0 /int1 are falling/rising edge selectable triggers. ht46r63/ht46c63 rev. 1.90 4 may 17, 2004

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pin name i/o option description osc1 osc2 i o rc or crystal a resistor across osc1 and vdd or a crystal across osc1 and osc2 will generate a system clock. osc3 osc4 i o 32768hz crystal across osc3 and osc4 will generate rtc clock signal which only provides system timing. cmpn i negative input for comparator cmpp i positive input for comparator cmpo o comparator output chgo o comparator output with 32768hz carrier vdd positive power supply avdd a/d converter positive power supply, avdd should be externally con - nected to vdd vss negative power supply, ground res i schmitt trigger reset input vlcd i/o lcd highest voltage; should be connected to vdd with external resistor. seg0~seg18 o seg7~seg18 logical cmos lcd segment signal driving outputs seg7~seg10 can be optioned as out - put lines. seg11~seg14, seg15~seg18 can be optioned as a high sink - ing output lines. com0~com2 com3/seg19 o com3 or seg19 lcd common signal driving outputs absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (rc osc) (analog circuit disabled) 3v no load, f sys =4mhz 12 ma 5v 35 i dd2 operating current (rc osc) 3v no load, f sys =4mhz 12 ma 5v 35 i dd3 operating current 5v no load, f sys =8mhz 35ma i stb1 standby current (wdt osc on, rtc off, lcd off) 3v no load, system halt 5 a 5v 15 i stb2 standby current (wdt osc off, rtc off, lcd off) 3v system halt 1 a 5v 1 ht46r63/ht46c63 rev. 1.90 5 may 17, 2004
symbol parameter test conditions min. typ. max. unit v dd conditions i stb3 standby current (wdt osc off, rtc on, lcd off) 3v system halt 5 a 5v 15 i stb4 standby current (wdt osc off, rtc on, lcd on with low current internal r type bias option) 3v system halt v lcd =v dd 10 12 16 a 5v 20 24 32 i stb5 standby current (wdt osc off, rtc on, lcd on with middle current internal r type bias option) 3v system halt v lcd =v dd 16 20 26 a 5v 32 40 52 i stb6 standby current (wdt osc off, rtc on, lcd on with high current internal r type bias option) 3v system halt v lcd =v dd 38 52 68 a 5v 76 104 136 v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd 3v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lcd lcd highest voltage 0 v dd v i oh1 i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 8 i ol1 i/o port sink current 3v v ol =0.1v dd 612 ma 5v 10 25 i oh2 seg7~18 logical source current 3v v oh =0.9v dd 2 4 ma 5v 4 8 i ol2 seg7~10 logical sink current 3v v ol =0.1v dd 8 ma 5v 16 i ol3 seg11~18 logical sink current 3v v ol =0.1v dd 16 ma 5v 32 i ohtotal i/o port total source current 100 ma i oltotal i/o port total sink current 100 ma r ph pull-high resistance (i/o) 3v 20 60 100 k 5v 10 30 50 v os comparator input offset voltage 10 10 mv v i comparator input voltage range 0.2 v dd 0.8 v v ad a/d input voltage 0 v dd v e ad a/d conversion integral nonlinearity error 0.5 1 lsb i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma ht46r63/ht46c63 rev. 1.90 6 may 17, 2004
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 f sys2 system clock (32768hz crystal osc) 2.2v~5.5v 32768 hz f timer timer input frequency 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 t wdt watchdog time-out period note: t sys =4/f sys 65536 t sys or 65536 t wdtosc or 65536 t rtcosc t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 64 t ad t adcs a/d sampling time 32 t ad t comp response time of comparator 3 s note: t sys =1/f sys ht46r63/ht46c63 rev. 1.90 7 may 17, 2004
ht46r63/ht46c63 rev. 1.90 8 may 17, 2004

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> - # $ , ' ( execution flow mode program counter *11~*8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000 00000000 external interrupt 0 0000 00000100 external interrupt 1 0000 00001000 timer/event counter overflow 0000 00001100 time base time-out 0000 00010000 a/d interrupt 0000 00010100 rtc interrupt 0000 00011000 skip pc+2 loading pcl @11~@8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11~#8 #7 #6 #5 #4 #3 #2 #1 #0 return (ret, reti) s11~s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits functional description execution flow the system clock for the microcontroller is derived from an external rc or crystal oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of 4 system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch and decoding takes an instruction cy - cle while execution take the next instruction cycle. how - ever, the pipelining scheme causes each instruction to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to com - plete the instruction. program counter pc the program counter controls the sequence in which the instructions stored in the program memory are executed and its contents specify full range of program memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl (program counter lower-order byte register), subroutine call, initial reset, interrupts or return from subroutine or interrupts, the program counter ma - nipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower-order byte of the program counter (pcl) can be accessed by using software instructions. moving da ta into the pcl performs a short jump. the destina - tion will be within the current program rom page. once the control transfer takes place, the execution suf - fers from having an additional dummy cycle. program memory prom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into
ht46r63/ht46c63 rev. 1.90 9 may 17, 2004 4096 15 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the external interrupt 0 ser - vice program. if the int0 input pin is activated, the in - terrupt is enabled and the stack is not full, the program begins execution at this location. location 008h this area is reserved for the external interrupt 1 ser - vice program. if the int1 input pin is activated, the in - terrupt is enabled and the stack is not full, the program begins execution at this location. location 00ch this area is reserved for the timer/event counter inter - rupt service program. if a timer interrupt results from a timer/event counter overflow, and the interrupt is en - abled and the stack is not full, the program begins ex - ecution at location 00ch. location 010h this area is reserved for the time base interrupt ser- vice program. if the a time base time-out occurs, the interrupt is enabled and the stack is not full, the pro- gram begins execution at this location. location 014h this area is reserved for the a/d converter interrupt service program. if the interrupt is activated (when the a/d conversion is completed), the interrupt is enabled and the stack is not full, the program begins execution at this location. location 018h this area is reserved for the rtc interrupt service program. when the rtc time-out occurs, the interrupt is enabled and the stack is not full, the program begins execution at this location. table location any location in the program memory can be used as look-up tables. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to lower portion of tblh(08h) and the remaining bits (1 bits) of tblh are read as 0 . the table pointer (tblp) is read/write register (07h), which indicates the table location. before accessing the table, the location has to be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr(interrupt service routine) both em- ploy the table read instruction, the contents of tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors are thus brought about. given this, using the table read in- struction in the main routine and the isr simulta- neously should be avoided. however, if the table read instruction has to be applied in both main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh in the main routine has been backup. all ta - ble related instructions require two cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of memory, which is used to save the contents of the program counter only. the stack is organized into 8 levels and is neither part of the data not programmable space, and is not accessible. the acti - vated level is indexed by the stack pointer and is not ac - ? & # - " 7 ; ; ; 7 " ; ; 7 $ > $ + & ' $ " & # & , & @ # & " 6 < # $ " , " # $ ! % # ! ? ! # & " $ & $ 6 + $ " # ! " # $ " # $ ! % # ! ? ! # & " $ * ( 4 ! % ? , $ /
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: 1 - 0 # $ a " " $ - # ; 7 7 ) 7 . " + $ # $ 6 " # $ ! % # ! ? ! # & " $ & $ 4 ! # " # $ ! % # - ! ? ! # & " $ 7 7 ; 7 6 < # $ " , " # $ ! % # ! ? ! # & " $ & $ - $ & $ 4 ! # " # $ ! % # ! ? ! # & " $ 7 ) 7 program memory instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: *11~*0: table location bits p11~p8: current program counter bits @7~@0: table pointer bits
ht46r63/ht46c63 rev. 1.90 10 may 17, 2004 cessible. at a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the stack pointer will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decreased (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow allow - ing the programmer to use the structure more easily. in similar case, if the stack is full and a call is subse - quently executed, stack overflow occurs and the first en - try will be lost (only the most recent 8 return addresses are stored). data memory ram the data memory is designed with 239 8 bits. the data memory is divided into two functional groups: spe - cial function registers and general purpose data mem - ory (208 8). most are read/write, but some are read only. the special function registers include the indirect ad- dressing register 0 and 1 (r0;00h, r1;02h), memory pointer 0 and 1 (mp0;01h, mp1;03h), bank pointer (bp:04h), accumulator (acc;05h), program counter lower-order byte register (pcl;06h), table pointer (tblp;07h), table higher-order byte register (tblh;08h), real time clock control register (rtcc;09h), status register (status;0ah), interrupt control register (intc0;0bh), timer higher-order byte register (tmrh;0ch), timer lower-order byte register (tmrl;0dh), timer control register (tmrc;0eh), i/o port data registers (pa;12h, pb;14h, pc;16h, pd;18h), i/o port control registers (pac;13h, pbc;15h, pcc;17h, pdc;19h), pwm0 (1ah), pwm1 (1bh), pwm2 (1ch), pwm3 (1dh), intc1 (1eh),the a/d re - sult register (adr;21h), the a/d control register (adcr;22h) and the a/d clock setting register (acsr;23h). the remaining space before the 30h is re - served for future expansion and reading these locations will return the result 00h . the general-purpose data memory, addressed from 30h to ffh, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and cleared by set [m].i and clr [m].i , respectively. they are also indirectly acces - sible through memory pointers (mp0 and mp1). indirect addressing register location 00h (02h) is indirect addressing registers that are not physically implemented. any read/write opera - tion of [00h] ([02h]) will access data memory pointed to by mp0 (mp1). reading location 00h (02h) itself indi - rectly will return the result 00h . writing indirectly re - sults in no operation. the memory pointers are 8-bit registers. only the mp1/r1 can be used to access the lcd ram (bp=1). % $ ' & , ! % - $ . . 6 7 7
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ht46r63/ht46c63 rev. 1.90 11 may 17, 2004 bank pointer the bank pointer is used to assign the accessed ram bank. when the users want to access the ram bank 0 a 0 should be loaded onto bp. when the bp is equal to 1 , the lcd ram will be accessed (use mp1/r1 indi - rect addressing only). ram locations before 40h in any bank are overlapped. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addi - tion operations related to the status register may give different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt in - struction. the pdf flag can be affected only by exe - cuting the halt or clr wdt instruction or a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. interrupt the microcontroller provides two external interrupts, an internal timer/event counter overflow interrupt, a time base time-out interrupt, an a/d converter end-of-conversion interrupt and a real time clock time-out interrupt. the interrupt control registers (intc0: 0bh and intc1: 1eh) contains the interrupt control bits to set the enable or disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flags are recorded. if a certain interrupt requires servicing within the service routine, the programmer may set the emi and the corresponding bit of intc0/intc1 to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is de - creased. if immediate service is desired, the stack has to be prevented from becoming full. labels bits function c0 c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa; otherwise ov is cleared. pdf 4 pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by exe - cuting the halt instruction. to 5 to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status register
ht46r63/ht46c63 rev. 1.90 12 may 17, 2004 all these kinds of interrupts have the wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified location(s) in the program memory. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which corrupts the desired control sequence, the pro - grammer should save these contents first. external interrupts are triggered by a high to low and/or low to high transition of int0 /int1 and the related inter - rupt request flag (bit 4/5 of intc0 ) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 004h/008h will occur. the external interrupt request flag and emi bits will cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (bit 6 of intc0), caused by a timer overflow. when the inter - rupt is enabled, the stack is not full and the timer/event counter interrupt request flag is set, a subroutine call to location 00ch will occur. the related interrupt request flag will be reset and the emi bit cleared to disable fur - ther interrupts. the time base time-out interrupt is initialized by setting the time base time-out interrupt request flag (bit 4 of intc1), caused by a time base time-out. when the in- terrupt is enabled, the stack is not full and the time base time-out interrupt request flag is set, a subroutine call to location 010h will occur. the related interrupt request flag will be reset and the emi bit cleared to disable fur- ther interrupts. the a/d converter end-of-conversion interrupt is initial- ized by setting the a/d end-of-conversion interrupt re - quest flag (bit 5 of intc1), caused by an end of a/d conversion. when the interrupt is enabled, the stack is not full and the end of a/d conversion interrupt request flag is set, a subroutine call to location 014h will occur. the related interrupt request flag will be reset and the emi bit cleared to disable further interrupts. the real time clock time-out interrupt is initialized by set - ting the real time clock interrupt request flag (bit 6 of intc1), caused by a rtc time-out. when the interrupt is enabled, the stack is not full and the rtc time-out in - terrupt request flag is set, a subroutine call to location 018h will occur. the related interrupt request flag will be reset and the emi bit cleared to disable further inter - rupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between rising edge of two consecutive t2 pulses, will be serviced on the later of the two t2 pulses, if the corresponding interrupts are enabled. in the case of simultaneous requests the priorities in the follow table apply. these can be masked by clearing the emi bit. interrupt source priority vector external interrupt 0 1 004h external interrupt 1 2 008h timer/event counter overflow interrupt 3 00ch time base time-out interrupt 4 010h end of a/d conversion interrupt 5 014h rtc time-out interrupt 6 018h the external interrupt 0/1 request flags (ei0f/ei1f), timer/event counter interrupt request flag (tf), time base interrupt request flag (tbf), a/d converter inter - rupt request flag (adf), rtc interrupt request flag (rtf), enable external interrupt 0/1 (ee0i/ee1i), enable timer/event counter interrupt bit (eti), enable time base interrupt (etbi), enable a/d converter interrupt (eadi), enable rtc interrupt (erti) and enable master inter - rupt bit(emi) constitute interrupt control registers (intc0/intc1) which is located at 0bh/1eh in the data memory. emi, ee0i, ee1i, eti, eadi and erti are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupts from being serviced. once the interrupt request flags (ei0f, ei1f, tf, tbf, adf, rtf) are set, they will remain in the intc0/intc1 until the interrupts are serviced or cleared by software instructions. it is suggested that a program does not use the call within a interrupt subroutine. it because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the call operates in the interrupt subroutine. the defini - tions of intc0 and intc1 registers are as shown. bit no. label function intc0 register 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei0 controls the external interrupt 0 (1= enabled; 0= disabled) 2 eei1 controls the external interrupt 1 (1= enabled; 0= disabled) 3 eti controls the timer/event counter over - flow interrupt (1= enabled; 0= disabled) 4 eif0 external interrupt 0 request flag (1= active; 0= inactive)
ht46r63/ht46c63 rev. 1.90 13 may 17, 2004 bit no. label function 5 eif1 external interrupt 1 request flag (1= active; 0= inactive) 6tf timer/event counter overflow request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc1 register 0 etbi controls the time base interrupt (1= enabled; 0= disabled) 1 eadi controls the a/d converter interrupt (1= enabled; 0= disabled) 2 erti controls the real time clock interrupt (1= enabled; 0= disabled) 3 unused bit, read as 0 4 tbf time base time-out interrupt 0 request flag (1= active; 0= inactive) 5 adf end of a/d conversion interrupt request flag (1= active; 0= inactive) 6 rtf rtc time-out interrupt request flag (1= active; 0= inactive) 7 unused bit, read as 0 oscillator configuration there are four oscillator circuits implemented in the mi- cro-controller. two of them are designed for system clocks, namely the external rc oscillator and the crystal oscillator, which are determined by options. the halt mode stops the system oscillator and resists the external signal to con - serve power. another one is a 32768hz crystal oscilla - tor, which only provides use for real time clock. the other one is a built-in 12khz rc oscillator, which is used for wdtosc. if the system clock uses the external rc oscillator, an external resistor between osc1 and vdd is required and the resistance should range from 24k to 1m . the system clock, divided by 4, is available on osc2, which can be used to synchronize external logic. if the system clock uses the crystal oscillator, a crystal across osc1 and osc2 is needed to provide the feed - back and phase shift required for the oscillator, and no other external components are demanded. instead of a crystal, the resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. if the rtcosc is used, a crystal across osc3 and osc4 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. watchdog timer wdt the clock source of wdt (and lcd, rtc, time base ) is implemented by a dedicated crys tal oscillator (32.768khz: rtcosc) or instruction clock (system fre- quency divided by 4: f sys /4) or a dedicated rc oscillator (12khz:wdtosc) decided by options. this timer is de- signed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable ! " #
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ht46r63/ht46c63 rev. 1.90 14 may 17, 2004 results. the watchdog timer can be disabled by options. if the watchdog timer is disabled, all the executions re - lated to the wdt result in no operation. the wdt time-out period is fixed as 2 16 /f s . the f s means the clock frequency of wdt, time base, rtc and lcd. if wdtosc is selected as the wdt clock, the time-out period may vary with temperatures, vdd and process variations. the wdtosc and rtcosc can be still run - ning (decided by option) at the halt mode if they are se - lected as the wdt clock source. once the 32.768khz oscillator (with a period of 31.25 s normally) is selected to be the clock source of wdt (and lcd, rtc, time base), it is directly divided by 2 16 to get the nominal time-out period of 2 seconds. if the wdt clock comes from the instruction clock, the wdt will stop counting and lose its protecting purpose in halt mode. in this situ - ation the logic can only be restarted by external logic. if the device operates in a noisy environment, using the rtcosc or wdtosc is strongly recommended, since the halt will stop the system clock. the overflow of wdt under normal operation will initial - ize chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset , and only the pc and sp are reset to zero. to clear the contents of wdt , 3 methods are adopted; external re - set (a low level to res ) , software instruction(s) and a halt instruction. the software instruction(s) include clr wdt and the other set clr wdt1 and clr wdt2 of these two types of instruction, only one can be active depending on the options clr wdt times selection option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clr wdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may re - set the chip as a result of time-out. the rtc oscillator should be designed as an auto-speed-up oscillator. af - ter the rtc oscillator is oscillating, the auto-speed-up should be turned off. time base generator there is a time base generator implemented in the mi - cro-controller. the time base generator provides time-out periods selection whose range from f s /2 12 to f s /2 15 . when the time base time-out occurs and the stack is not full and the time base interrupt is enabled, an interrupt subroutine call to rom location 010h will activate. rtc generator there is an rtc generator implemented in the mi - cro-controller. the rtc generator provides software configurable real time clock periods whose range from f s /2 8 to f s /2 15 . when the rtc time-out occurs and the stack is not full and the rtc interrupt is enabled, an in - terrupt subroutine call to rom location 018h will acti - vate. the rtcc is the real time clock control register used to select the division ratio of rtc clock sources. rtcc.7~rtcc.3 cannot be used. rtcc.2 rtcc.1 rtcc.0 rtc clock divided factor 000 2 8 001 2 9 010 2 10 011 2 11 100 2 12 101 2 13 110 2 14 111 2 15 power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdtosc or rtcosc will stop or keep running de - cided by option (if the wdtosc or rtcosc is se - lected) the contents of the on-chip ram and registers remain unchanged. wdt will be cleared and recounted again (if the wdt clock is from the wdtosc or rtcosc). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig- nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or execut - ing the clr wdt instruction and is set when execut - ing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the pc and sp; the others keep their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by the option. awakening from an i/o port stimu - lus, the program will resume execution of the next in - struction. if it is awakening from an interrupt, two sequences may happen. if the related interrupt is dis - abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regu - lar interrupt response takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled.
ht46r63/ht46c63 rev. 1.90 15 may 17, 2004 once a wake-up event occurs, it takes 1024 t sys (sys - tem clock period) to resume normal operation. in other words, a dummy period will be inserted after wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. the 32.768khz crystal oscillator still run or stop in the halt mode. (decided by option) reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the pc and sp, leaving the other cir - cuits in their original state. some registers remain un - changed during other reset conditions. most registers are reset to the initial condition when the reset condi - tions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u means unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay to delay 1024 system clock pulses when system power-up or the system awakes from the halt state. when the system power-up occurs, the sst delay is added during the reset period. but when the reset co - mes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. an extra option load time delay is added during system reset (power-up, wdt time-out at normal mode or res reset). the chip reset statuses of the functional units are as shown. pc 000h interrupt disable wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode sp points to the top of the stack # 6 5 & $ 4 ! # 2 & % $ - $ # reset timing chart $ - $ # 7 . * , 1 $ - $ # 6 > - # $ $ - $ # 4 ? & # & % % , $ ! " # $ reset configuration 6 5 ( ( e ; f e ; f reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference.
ht46r63/ht46c63 rev. 1.90 16 may 17, 2004 the registers states are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res rese (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pch.pcl 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu rtcc --xx x111 --xx x111 --xx x111 --xx x111 --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu tmrl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 0--- -100 0--- -100 0--- -100 0--- -100 u--- -uuu note: * stands for warm reset u stands for unchanged x stands for unknown
ht46r63/ht46c63 rev. 1.90 17 may 17, 2004 timer/event counter a timer/event counter is implemented in the device. the timer/event counter contains a 16-bit programmable count-up counter and the clock may come from an ex - ternal source or the internal clock source. the internal clock source is the system clock divided by 4: f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are 3 registers related to timer/event counter; tmrh(0ch), tmrl(0dh), tmrc(0eh). writing tmrl only stores the data into a low byte buffer, and writing tmrh will put the written data and the low contents of low byte buffer to preload register (16 bits) simulta - neously. the timer/event counter preload register is changed by writing tmrh operations and writing tmrl will keep the timer/event counter preload register un - changed. reading tmrh will also latch the tmrl into the low byte buffer to avoid the false timing problem. reading tmrl returns the contents of the low byte buffer. in other words, the low byte of timer/event counter cannot be read directly. it has to read the tmrh first to make the low byte contents of timer/event counter latched into the buffer. the tmrc is the timer/event counter control register, which defines the operating mode, counting en- able or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from f sys /4. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on f sys /4. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the corresponding interrupt request flag (tf; bit 6 of intc0) at the same time. in pulse width measurement mode with the ton and te bits are equal to one, once the tmr has received a tran - sition from low to high (or high to low if the te bit is 0) it will start counting until the tmr returns to the original level and reset the ton. the measured result will re - main in the timer/event counter even if the activated transition occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transition pulse. note that, in this operat - ing mode, the timer/event counter starts counting not according to the logic level but according to the transi - tion edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload regis - ter and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be cleared automati - cally after the measurement cycle is complete. but in the other two modes the ton can only be reset by instruc - tions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the operation mode is, writin ga0toetican disabled the correspond- ing interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also load the data to timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. the timer/event counter will still operate until the overflow occurs (a timer/event counter reloading will occur at the same time). 6 ! , - $ & 1 # 2 $ - ! $ $ " # 1 $ " # , 4 & # & $ $ + $ " # ! " # $ $ , 1 $ & - # $ ) 4 & # * : > # $ ! $ # ! - $ , 1 4 & # & $ $ + $ " # ! " # $ / 7 8 * 0 + $ , : # " # $ ! % # timer/event counter
ht46r63/ht46c63 rev. 1.90 18 may 17, 2004 when the timer/event counter (reading tmrh) is read, the cl ock will be blocked to avoid errors. as this may re - sults in a counting error, this must be taken into consid - eration by the programmer. label (tmrc) bits function 0~2 unused bits, read as 0 te 3 to define the active edge of tmr pin in - put signal (0=active on low to high; 1=active on high to low) ton 4 to enable or disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 tm0 tm1 6 7 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc register input/output ports there are 32 bi-directional input/output lines in the mi - cro-controller, labeled from pa to pd, which are mapped to the data memory of [12h], [14h], [16h] and [18h], re- spectively. all of these i/o ports can be used as input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h or 18h). for output operation, all the data is latched and remains unchanged until the output latch is rewrit - ten. each i/o line has its own control register (pac, pbc, pcc, pdc) to control the input/output configuration. with this control register, cmos output or schmitt trig - ger input with or without (depends on options) pull-high resistor structures can be reconfigured dynamically (i.e., on-the fly) under software control. to function as an in - put, the corresponding latch of the control register has to be set as 1 . the pull-high resistor (if the pull-high re - sistor is enabled) will be exhibited automatically. the in - put sources are also dependent on the control register. if the control register bit is 1 , the input will read the pad state ( mov and read-modify-write instructions). if the control register bit is 0 , the contents of the latches will move to internal data bus ( mov and read-modify-write instructions). the input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h and 19h. after a chip reset, these input/output lines stay at a high level (pull-high options) or floating state (non-pull-high options). each bit of these input/output latches can be set or cleared by set [m].i (m=12h, 14h, 16h or 18h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i clr [m].i , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), 5 ( $ 4 ! % % # & " - " # $ ! % # > - # $ ( $ 4 ! % / . " , > 0 $ 1 # $ & - # $ g h g h g " # , & # 7 # ! - & # $ " # , $ & - # $ 2 & % $ - $ # $ 1 " # , $ & - # $ & # $ # $ & - # $ # & # . . g / " , > 0 ! , - $ 3 $ " $ # & - ? , $ 7 & 2 * : 7 & 2 4 * : 6 1 $ # ! , - $ " 1 input/output ports
ht46r63/ht46c63 rev. 1.90 19 may 17, 2004 and then write the results back to the latches or the ac - cumulator. each line of port a has the capability of waking-up the device. the pull-high resistor of each i/o line is decided by options. comparator there is a comparator implemented in this microcontroller. this comparator can be enabled/dis - abled by options. its inputs are cmpp(+) and cmpn(-) and outputs are cmpo and chgo. when the cmpn in - put level is less than the level of cmpp, the cmpo out - put is v dd . when the cmpn input level is higher than the level of cmpp, the cmpo output is v ss . the chgo signal is combined with cmpo and 32768hz carrier if 32768hz rtc oscillator is applied. this comparator also can be disabled by options. when the system enters halt mode, the comparator is disabled to reduce power consumption. once the comparator is disabled, the chgo and cmpo will stay at vss level. lcd display memory the micro-controller provides an area of embedded data memory for lcd driver. this area is located from 40h to 53h of he ram bank 1. bank pointer (bp; lo- cated at 04h of the ram) is the switch between the gen- eral purpose ram and the lcd display memory. when the bp is set to 1 , any data written into 40h~53h (indi- rect accessing by using the mp1and r1) will effect the lcd display. when the bp is cleared to 0 , any data written into 40h to 53h will access the general purpose data memory. the lcd display memory can be read and written to only by indirect addressing mode using mp1. when data is written into the display data area it is automatically read by the lcd driver which then gener - ates the corresponding lcd driving signals. to turn the display on or off, an 1 or a 0 is written to the corre - sponding bit of the display memory, respectively. the figure illustrates the mapping between the display mem - ory and lcd pattern for the micro-controller. lcd driver output and bias circuit the output number of the micro-controller lcd driver can be 2 0 3or19 4 by options (ie., 1 / 3 duty or 1 / 4 duty). the bias type of lcd driver is r type, no exter - nal capacitor is required. the lcd can be optioned as lcd on at halt or lcd off at halt which are de - pendent on options. the seg7~seg18 also can be optioned as logical out - puts. each group of seg7~seg10, seg11~seg14 and seg15~seg18 can be optioned individually. once an lcd segment is optioned as a logical output, the con - tents of bit 0 of the related segment address in lcd ram will appear on the segment. memory segment output bit 0=0 bit 0=1 vss vdd logical output function 7 6 3 6 7
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ht46r63/ht46c63 rev. 1.90 21 may 17, 2004 a/d converter the 8 channels and 8-bit resolution (7-bit accuracy) a/d converter are implemented in this microcontroller. the reference voltage is avdd. the avdd pin must be con - nected to vdd externally. conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly coupled power supply lines. the a/d converter contains 3 special registers which are; adr (21h), adcr (22h) and acsr (23h). the adr is a/d result register. after the a/d conversion is completed, the adr should be read to get the conver- sion result data. the adcr is an a/d converter control register, which defines the a/d channel number, analog channel select, start a/d conversion control bit and the end of a/d conversion flag. if the users want to start an a/d conversion, after select the converted analog chan - nel, and then give start bit a positive pulse (0
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0). at the end of a/d conversion, the eocb bit is cleared and an a/d converter interrupt occurs(if the a/d con - verter interrupt is enabled). the acsr is an a/d clock setting register, which is used to select the a/d clock source. the a/d converter control register is used to control the a/d converter. the bit2~bit0 of the adcr are used to select an analog input channel. there are a total of 8 channels to select. the bit5~bit3 of the adcr are used to set pb configurations. pb can be an analog input or as digital i/o line decided by these 3 bits. once a pb line is selected as an analog input, the i/o functions and pull-high resistor of this i/o line are disabled. the eocb bit (bit 6 of the adcr) is end of a/d conversion flag. check this bit to know when a/d conversion is com- pleted. the start bit of the adcr is used to begin the conversion of a/d converter. give start bit a falling edge that means the a/d conversion has started. the a/d converter remains in reset state while the start stays at 1 . in order to ensure the a/d conversion is completed, the start should stay at 0 until the eocb is cleared to 0 (end of a/d conversion). the bit 7 of the acsr is used for testing purpose only. it can not be used for the users. the bit1 and bit0 of the acsr are used to select a/d clock sources. when the a/d conversion is completed, the a/d inter - rupt request flag is set. the bit is set to 1 when the start bit is set to 1 . register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adr d7 d6 d5 d4 d3 d2 d1 d0 & - ' ! $ " # / , : 8 & 1 1 , $ 2 & 2 0 & - - $ , $ ' # ? , $ ? > ' 1 $ % # & " e * a 5 i 5 i 5
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ht46r63/ht46c63 rev. 1.90 22 may 17, 2004 label (adcr) bits functions acs0 acs1 acs2 0 1 2 acs2, acs1, acs0: a/d channel selection 0,0,0: an0 0,0,1: an1 0,1,0: an2 0,1,1: an3 1,0,0: an4 1,0,1: an5 1,1,0: an6 1,1,1: an7 pcr0 pcr1 pcr2 3 4 5 pcr2, pcr1, pcr0: pb7~pb0 pad functions 0,0,0: pb7, pb6, pb5, pb4, pb3, pb2, pb1, pb0 0,0,1: pb7, pb6, pb5, pb4, pb3, pb2, pb1, an0 0,1,0: pb7, pb6, pb5, pb4, pb3, pb2, an1, an0 0,1,1: pb7, pb6, pb5, pb4, pb3, an2, an1, an0 1,0,0: pb7, pb6, pb5, pb4, an3, an2, an1, an0 1,0,1: pb7, pb6, pb5, an4, an3, an2, an1, an0 1,1,0: pb7, pb6, an5, an4, an3, an2, an1, an0 1,1,1: an7, an6, an5, an4, an3, an2, an1, an0 eocb 6 end of a/d conversion flag (0: end of a/d conversion) start 7 a/d conversion sequence (start=010) 0: initial value after chip reset 0
1: initial next a/d conversion. 1: reset a/d converter and set eocb to 1 1
0: starts the a/d conversion. 0: normal state for a/d note: it is recommended that start is 0 and pcr2~pcr0 is 000 before mcu entering halt mode. halt will not standby the a/d converter automatically. acsr register label (acsr) bits functions adcs0 adcs1 0 1 adcs1, adcs0: selects the a/d converter clock source 0,0: f sys /2 0,1: f sys /8 1,0: f sys /32 1,1: cannot be used cmpc 2 comparator control (*) 0: disable 1: enable 3~6 unused bit, read as 0 test 7 for test mode used only 0: normal mode 1: test only, cannot be used note: * this bit is 0 during reset.
ht46r63/ht46c63 rev. 1.90 23 may 17, 2004 the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using eocb polling method to detect end of conversion clr intc0.3 ; disable a/d interrupt in interrupt control register mov a,00100000b mov adcr,a ; setup adcr register to configure port pb0~pb3 as a/d inputs and select ; an0 to be connected to the a/d converter mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock start_conversion: clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d polling_eoc: sz adcr.6 ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adr ; read conversion result from the high byte adr register mov adr_buffer,a ; save result to user defined register : : jmp start_conversion ; start next a/d conversion example: using interrupt method to detect end of conversion set intc0.0 ; interrupt global enable set intc0.3 ; enable a/d interrupt in interrupt control register mov a,00100000b mov adcr,a ; setup adcr register to configure port pb0~pb3 as a/d inputs and select ; an0 to be connected to the a/d converter mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock start_conversion: clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d : : ; interrupt service routine eoc_service routine: mov a_buffer,a ; save acc to user defined register mov a,adr ; read conversion result from the high byte adr register mov adr_buffer,a ; save result to user defined register clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d mov a,a_buffer ; restore acc from temporary storage reti
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ht46r63/ht46c63 rev. 1.90 25 may 17, 2004 options the following table shows all kinds of options in the microcontroller. all of the options must be defined to ensure proper system function. no. options 1 pa wake-up enable or disable (1/0) options 2 wdt/lcd/rtc/time base clock source (f s ): rtcosc(32768hz crystal), t1d or wdtosc (*1) 3 clr wdt instructions: 1/2 4 wdt enable or disable 5 pa pull-high enable or disable (1 optio n : 4 bits (0~3/4~7)) 6 pb pull-high enable or disable (1 optio n : 4 bits (0~3/4~7)) 7 pc pull-high enable or disable (1 optio n : 4 bits (0~3/4~7)) 8 pd pull-high enable or disable (1 optio n : 4 bits (0~3/4~7)) 9 int0 or int1 trigger edge: disable; high to low; low to high; low to high or high to low. 10 com3 or seg19 (1 / 4or1 / 3 duty) 11 lcd on/off at halt mode 12 enable or disable comparator 13 enable or disable pwmi function for pdi (bit optional) 14 f s /2 12 ~f s /2 15 : time base period 15 seg7~seg18 logical or lcd output (1 option: 4 bits (seg7~seg10/seg11~seg14/seg15~seg18)) 16 system oscillators: external rc/ external crystal 17 enable or disable rtcosc(32.768khz crystal) or wdtosc at halt mode 18 lcd bias current: low/middle/high driving current 19 lcd driver clock selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 , f s stands for the clock source selection by options. note: *1 t1d is stopped at halt; rtcosc(32.768khz crystal) and wdt osc are stopped or non-stopped at halt decided by option(18).
application circuits the following table shows the c1, c2 and r1 value according different crystal values. crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k 4mhz resonator (3 pin) 0pf 12k 4mhz resonator (2 pin) 10pf 12k 3.58mhz crystal 0pf 10k 3.58mhz resonator (2 pin) 25pf 10k 2mhz crystal & resonator (2 pin) 25pf 10k 1mhz crystal 35pf 27k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. ht46r63/ht46c63 rev. 1.90 26 may 17, 2004 . .
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instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht46r63/ht46c63 rev. 1.90 27 may 17, 2004
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht46r63/ht46c63 rev. 1.90 28 may 17, 2004
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 29 may 17, 2004
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 30 may 17, 2004
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 31 may 17, 2004
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 32 may 17, 2004
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 33 may 17, 2004
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 34 may 17, 2004
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 35 may 17, 2004
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 36 may 17, 2004
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 37 may 17, 2004
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 38 may 17, 2004
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 39 may 17, 2004
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 40 may 17, 2004
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht46r63/ht46c63 rev. 1.90 41 may 17, 2004
package information 56-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 720 730 d89 99 e 25 f4 10 g25 35 h4 12 0 8 ht46r63/ht46c63 rev. 1.90 42 may 17, 2004 .
9
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100-pin qfp (14 20) outline dimensions symbol dimensions in mm min. nom. max. a 18.50 19.20 b 13.90 14.10 c 24.50 25.20 d 19.90 20.10 e 0.65 f 0.30 g 2.50 3.10 h 3.40 i 0.10 j1 1.40 k 0.10 0.20 0 7 ht46r63/ht46c63 rev. 1.90 43 may 17, 2004 ) ) . 6 ; 3 7 m h
ht46r63/ht46c63 rev. 1.90 44 may 17, 2004 copyright 2004 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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